Resource Library
Standards
Test Method for Real-Time Soft Error Rate; JEDEC JESD89-1A, October 2007
Technical Papers
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 130 nm CMOS; Mohammad Sharifkhani, Manoj Sachdev; JSSCC Feb 2009
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor; Dan Krueger, Erin Francom, Jack Langsdorf; Intel, Fort Collins, CO; ISSCC 2008
SRAMs using a Compact Critical Charge Model; Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev, ISQED 2008
Dynamic Data Stability in Low-power SRAM Design; M. Sharifkhani, S. M. Jahinuzzaman, M. Sachdev; CICC, 2007.
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM; Mohammad Sharifkhani, Manoj Sachdev; IEEE Transaction on VLSI Systems, VOL. 15, NO. 2, FEBRUARY 2007.
A Low Power SRAM Architecture Based on Segmented Virtual Grounding; Mohammad Sharifkhani, Manoj Sachdev; ISLPED'06, October 2006.
Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology; Riaz Naseer, Rashed Zafar Bhatti, Jeff Draper; Proceeding of the 49th IEEE International Midwest Symposium on Circuits and Systems; University of Southern Califronia, August 2006
An analytical approach for soft error rate estimation of SRAM-based FPGAs; Ghazanfar Asadi, Mehdi B. Tahoori; International Symposium on Field Programmable Gate Arrays; North Eastern University, Boston MA, 2005
Soft Errors in Advanced Computer Systems; Robert Baumann, IEEE Design & Test, v.22 n.3, p.258-266, May 2005
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic",; Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi; International Conference on Dependable Systems and Networks, University of Texas Austin and IBM Austin Research Laboratory, 2002
Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies; Dodd, P.E.; Shaneyfelt, M.R.; Schwank, J.R.; Hash, G.L.; IEDM, p.333-336, 2002
Industry Articles on Soft Errors
Soft Errors Create Tough Problems; System Level Design, 28 April 2009
Intel plans to tackle cosmic ray threat; BBC News, Tuesday, 8 April 2008
Consumer ICs: Designing for Reliability, Michael Santarini, Electronic Design News, March 6, 2008
Intel shows off Silverthorne and Tukwila; Rupert Goodwins; ZDNet.co.uk, February 4, 2008
Understanding neutron single-even phenomena in FPGAs; Joe Fabula, Jason, Moore, Andrew Ware; Military Embedded Systems, 2007
Cosmic radiation comes to ASIC and SOC design, Michael Santarini; Electronic Design News, May 12, 2005
Soft Errors' Impact on System Reliability, Ritesh Mastipuramand Edwin C Wee; Electronic Design News, September 30, 2004
Neutron Swarm Swirls Around FPGA Reliability; Ron Wilson; EETimes, April 19, 2004
Strategy for reducing soft errors is needed; Mark-Eric Jones; EETimes, September 27, 2002
Soft errors a problem as SRAM geometries shrink; Jeanne Graham; Electronics Supply & Manufacturing, January 28, 2002
SRAM soft errors cause hard network problems; Anthony Cataldo; EETimes, August 17, 2001
CertiChip in the News
What Have You Got for Single-Event Upset? A DAC Breakfast at Tiffy's; Steve Leibson; Electronic Design News, June 17, 2008